1. Field of the Invention
The present invention relates to semiconductor supports and, more specifically, to a silicon support having its surface comprising wells having different crystallographic orientations.
2. Discussion of the Related Art
In integrated circuit manufacturing, it is typical to form, on the same silicon substrate, both N-channel metal-oxide-semiconductor transistors (MOS) and P-channel MOS transistors. It is known that faster P-channel MOS transistors are obtained in silicon of crystallographic structure (110) and faster N-channel MOS transistors are obtained in silicon of crystallographic structure (100).
Methods enabling to form, in the same silicon substrate, wells having one or the other of the above-mentioned orientations have thus been searched for.
FIG. 1A is a cross-section view of an initial structure for various methods used in the forming of wells of different orientations. A silicon layer 13 of crystallographic orientation (110) extends on a silicon substrate 11 of crystallographic orientation (100). Insulating walls 15 are formed in silicon layer 13 and delimit silicon wells W1 and W2. As an example, insulating walls 15 may be made of silicon oxide. FIG. 1B illustrates the result obtained by various known methods for forming wells of different orientations. In this drawing, silicon wells W1 have kept an orientation (110) and silicon wells W2 have been transformed and have an orientation (100).
A first method which can be envisaged to pass from the structure of FIG. 1A to the structure of FIG. 1B comprises etching upper silicon layer 13 in wells W2, then performing, in the openings thus formed, an epitaxy from substrate 11 of orientation (100). However, it is generally considered that current etch and epitaxy techniques do not enable forming, in wells W2, single-crystal silicon having an even upper surface. It is then necessary to perform an additional step to polish the upper silicon surface, for example, a chem./mech. polishing (CMP). However, CMP techniques induce surface defects which prevent the forming of quality MOS transistors. Such disadvantages of epitaxy techniques are especially discussed in U.S. Pat. No. 7,060,585 in relation with FIGS. 5G to 5I.
Various complex methods have then been provided. However, U.S. Pat. No. 7,060,585 describes a method for forming wells of different orientations which includes forming an amorphization implantation in wells W2, then performing an anneal at high temperature. This anneal enables extending crystallographic structure (100) of silicon substrate 11 into the amorphized areas. The structure of FIG. 1B is thus obtained. This method especially has two disadvantages. First, the amorphization step creates defects in the silicon wells W2, which are not totally eliminated during the anneal. To attenuate these defects, more or less effective additional processings must be carried out. Further, this method requires an anneal step at a very high temperature, on the order of 1200° C., which is particularly difficult to implement.